Introducing the xCORE-200

XMOS-xCORE-200-Microcontroller

The xCORE-200, the second generation of xCORE microcontrollers, provides more memory and more cores per chip resulting in greater performance and the ability to run more demanding applications. In addition to the xCORE-200, they have also released the eXplorerKIT, containing everything you need to start developing applications on the powerful xCORE-200, and the xCORE-200 Multichannel Audio Platform, providing audio development for USB (PC, OS X, iOS and Android) and networked audio designs.

Dual issue: The XS1 architecture issues a maximum of 1 instruction per clock cycle, xCORE-200 can issue 2 instructions per clock cycle. This means that, for a given clock frequency, xCORE-200 has twice the peak instruction issue rate.

64-bit load and store: Each memory cycle can now load 64b of instruction or data, compared to 32b on the XS1 architecture.

High priority logical cores: xCORE-200 allows some cores to have a higher priority in the scheduler. Groups of high priority cores and low priority cores will be scheduled in a round robin. Determinism is not affected.

Kernel mode: A kernel mode added to enable traditional RTOS to be ported more comprehensively to an xCORE logical core.

More memory: Four times as much instruction/data memory is made available to xCORE-200 applications.

More instructions: As well as adding load and store instructions for the wider word width, there are also additional instructions to accelerate common compression, extraction, DSP and timing functions.