The ZL40204/ZL40205 are LVPECL clock fanout buffers with six identical output clock drivers capable of operating at frequencies up to 750MHz. Inputs to the ZL40204 are externally terminated to allow use of precision termination components and to allow full flexibility of input termination. The ZL40204 can accept DC or AC coupled LVPECL, LVDS, CML or HCSL input signals; single ended input signals can also be accepted. The ZL40205 provides an internal input termination network for DC and AC coupled inputs; optional input biasing for AC coupled inputs is also provided. The ZL40205 can accept DC or AC coupled LVPECL and LVDS input signals, AC coupled CML or HCSL input signals, and single ended signals. The ZL40204/ ZL40205 are designed to fanout low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.